Datasheet

CONTENTS
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Title
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Contents vii
2.6.2 Instruction Set Summary .............................................................................. 2-19
2.7 Execution Timings............................................................................................ 2-23
2.7.1 MOVE Instruction Execution Timing .......................................................... 2-25
2.7.2 Execution Timings—One-Operand Instructions .......................................... 2-26
2.7.3 Execution Timings—Two-Operand Instructions.......................................... 2-27
2.7.4 Miscellaneous Instruction Execution Times................................................. 2-29
2.7.5 Branch Instruction Execution Times ............................................................ 2-30
2.8 Exception Processing Overview ....................................................................... 2-31
2.8.1 Exception Stack Frame Definition................................................................ 2-32
2.8.2 Processor Exceptions .................................................................................... 2-34
2.9 ColdFire Instruction Set Architecture Enhancements....................................... 2-36
Chapter 3
Hardware Multiply/Accumulate (MAC) Unit
3.1 Overview............................................................................................................. 3-1
3.1.0.1 MAC Programming Model......................................................................... 3-2
3.1.0.2 General Operation....................................................................................... 3-3
3.1.0.3 MAC Instruction Set Summary .................................................................. 3-4
3.1.0.4 Data Representation.................................................................................... 3-4
3.2 MAC Instruction Execution Timings.................................................................. 3-5
Chapter 4
Local Memory
4.1 Interactions between Local Memory Modules ................................................... 4-1
4.2 SRAM Overview ................................................................................................ 4-1
4.3 SRAM Operation ................................................................................................ 4-2
4.4 SRAM Programming Model............................................................................... 4-3
4.4.1 SRAM Base Address Registers (RAMBAR0/RAMBAR1)........................... 4-3
4.5 SRAM Initialization............................................................................................ 4-4
4.5.1 SRAM Initialization Code .............................................................................. 4-5
4.6 Power Management ............................................................................................ 4-6
4.7 Cache Overview.................................................................................................. 4-6
4.8 Cache Organization............................................................................................. 4-8
4.8.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified............. 4-8
4.8.2 The Cache at Start-Up..................................................................................... 4-9
4.9 Cache Operation................................................................................................ 4-11
4.9.1 Caching Modes ............................................................................................. 4-13
4.9.1.1 Cacheable Accesses .................................................................................. 4-14
4.9.1.2 Write-Through Mode (Data Cache Only)................................................. 4-14
4.9.1.3 Copyback Mode (Data Cache Only)......................................................... 4-14