Datasheet

2-6 MCF5407 User’s Manual
Features and Enhancements
2.1.2.2.3 Hardware Divide Unit
The hardware divide unit performs the following integer division operations:
• 32-bit operand/16-bit operand producing a 16-bit quotient and a 16-bit remainder
• 32-bit operand/32-bit operand producing a 32-bit quotient
• 32-bit operand/32-bit operand producing a 32-bit remainder
2.1.2.3 Harvard Memory Architecture
A Harvard memory architecture supports the increased bandwidth requirements of the V4
processor pipelines by providing separate configuration, access control, and protection
resources for data (operand) and instruction memory. The MCF5407 has separate
instruction and data buses to processor-local memories, eliminating conflicts between
instruction fetches and operand accesses.
2.1.3 Debug Module Enhancements
The ColdFire processor core debug interface supports system integration in conjunction
with low-cost development tools. Real-time trace and debug information can be accessed
through a standard interface, which allows the processor and system to be debugged at full
speed without costly in-circuit emulators. The MCF5407 debug unit is a compatible
upgrade to MCF52xx and MCF53xx debug modules with added breakpoint registers and
support for I/O interrupt request servicing while in emulator mode.
On-chip breakpoint resources include the following:
• Configuration/status register (CSR)
• Background debug mode (BDM) address attributes register (BAAR)
• Bus attributes and mask registers (AATR and AATR1)
• Breakpoint registers. These can be used to define triggers combining address, data,
and PC conditions in single- or dual-level definitions. They include the following:
— Four PC breakpoint registers (PBR, PBR1, PBR2, and PBR3)
— PC breakpoint mask register (PBMR)
— Two pairs of data operand address breakpoint registers (ABHR/ABLR and
ABLR1/ABHR1)
— Data breakpoint registers (DBR and DBR1)
— Data breakpoint mask registers (DBMR and DBMR1)
• Trigger event registers. These can be programmed to generate a processor halt or
initiate a debug interrupt exception. They include the following:
— Trigger definition register (TDR)
— Extended trigger definition register (XTDR)