Datasheet

Chapter 2. ColdFire Core 2-11
Programming Model
2.2.2.1 Status Register (SR)
The SR stores the processor status, the interrupt priority mask, and other control bits.
Supervisor software can read or write the entire SR; user software can read or write only
SR[7–0], described in Section 2.2.1.5, “Condition Code Register (CCR).” The control bits
indicate processor states—trace mode (T), supervisor or user mode (S), and master or
interrupt state (M). SR is set to 0x27xx after reset.
Table 2-3 describes SR fields.
Table 2-2. MOVEC Register Map
Rc[11–0] Register Definition
0x002 Cache control register (CACR)
0x004 Access control register 0 (ACR0)
0x005 Access control register 1 (ACR1)
0x006 Access control register 2 (ACR2)
0x007 Access control register 3 (ACR3)
0x801 Vector base register (VBR)
0xC04 RAM base address register 0 (RAMBAR0)
0xC05 RAM base address register 1 (RAMBAR1)
0xC0F Module base address register (MBAR)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
System byte Condition code register (CCR)
Field T — S M — I — X N Z V C
Reset 00100 111 000 —————
R/W R/W R R/W R/W R R/W R R/W R/W R/W R/W R/W
Figure 2-5. Status Register (SR)
Table 2-3. Status Field Descriptions
Bits Name Description
15 T Trace enable. When T is set, the processor performs a trace exception after every instruction.
13 S Supervisor/user state. Indicates whether the processor is in supervisor or user mode
0 User mode
1 Supervisor mode
12 M Master/interrupt state. Cleared by an interrupt exception. It can be set by software during execution
of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer.
10–8 I Interrupt priority mask. Defines the current interrupt priority. Interrupt requests are inhibited for all
priority levels less than or equal to the current priority, except the edge-sensitive level-7 request,
which cannot be masked.
7–0 CCR Condition code register. See Table 2-1.