Datasheet

2-26 MCF5407 User’s Manual
Execution Timings
Table 2-13 gives execution times for MOVE.L instructions accessing program-visible
registers of the MAC unit, along with other MOVE.L timings. Execution times for moving
contents of the ACC or MACSR into a destination location represent the best-case scenario
when the store instruction is executed and no load, MAC, or MSAC instructions are in the
MAC execution pipeline. In general, these store operations require only one cycle for
execution, but if they are preceded immediately by a load, MAC, or MSAC instruction, the
MAC pipeline depth is exposed and execution time is 3 cycles.
2.7.2 Execution Timings—One-Operand Instructions
Table 2-14 shows standard timings for single-operand instructions.
-(Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)
(d16,Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —
(d8,Ay,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
(xxx).w 1(1/0) 2(1/1) 2(1/1) 2(1/1) — — —
(xxx).l 1(1/0) 2(1/1) 2(1/1) 2(1/1) — — —
(d16,PC) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —
(d8,PC,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) — — —
#<xxx> 1(0/0) 1(0/1) 1(0/1) 1(0/1) — — —
Table 2-13. Miscellaneous Move Execution Times
Opcode <ea>
Effective Address
Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>
move.l <ea>,ACC 1(0/0) — — — — — — 1(0/0)
move.l <ea>,MACSR 6(0/0) — — — — — — 6(0/0)
move.l <ea>,MASK 5(0/0) — — — — — — 5(0/0)
move.l ACC,Rx 1(0/0) — — — — — — —
move.l MACSR,CCR 1(0/0) — — — — — — —
move.l MACSR,Rx 1(0/0) — — — — — — —
move.l MASK,Rx 1(0/0) — — — — — — —
moveq #imm,Dx ———— — — — 1(0/0)
mov3q #imm,<ea> 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) —
mvs <ea>,Dx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0)
mvz <ea>,Dx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0)
Table 2-12. Move Long Execution Times (Continued)
Source
Destination
Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl