Datasheet

Chapter 4. Local Memory 4-3
SRAM Programming Model
Accesses are attempted in the following order:
1. SRAM
2. Cache (if space is defined as cacheable)
3. External access
4.4 SRAM Programming Model
The SRAM programming model consists of RAMBAR0 and RAMBAR1.
4.4.1 SRAM Base Address Registers (RAMBAR0/RAMBAR1)
The SRAM modules are configured through the RAMBARs, shown in Figure 4-1.
• Each RAMBAR holds the base address of the SRAM. The MOVEC instruction
provides write-only access to this register from the processor.
• Each RAMBAR can be read or written from the debug module in a similar manner.
• All undefined RAMBAR bits are reserved. These bits are ignored during writes to
the RAMBAR and return zeros when read from the debug module.
• The valid bits, RAMBARn[V], are cleared at reset, disabling the SRAM modules.
All other bits are unaffected.
Figure 4-1. SRAM Base Address Registers (RAMBARn)
RAMBARn fields are described in detail in Table 4-1.
31 11 10 9 8 7 6 5 4 3 2 1 0
Field BA — WP D/I — C/I SC SD UC UD V
Reset — 0
R/W W for CPU; R/W for debug
Address CPU space + 0xC04 (RAMBAR0), CPU space + 0xC05 (RAMBAR1)
Table 4-1. RAMBARn Field Description
Bits Name Description
31–11 BA Base address. Defines the SRAM module’s word-aligned base address. Each SRAM module
occupies a 2-Kbyte space defined by the contents of BA. SRAM may reside on any 2-Kbyte
boundary in the 4-Gbyte address space.
10–9 — Reserved, should be cleared.
8 WP Write protect. Controls read/write properties of the SRAM.
0 Allows read and write accesses to the SRAM module
1 Allows only read accesses to the SRAM module. Any attempted write reference generates an
access error exception to the ColdFire processor core.
7 D/I Data/instruction bus. Indicates whether SRAM is connected to the internal data or instruction bus.
0 Data bus
1 Instruction bus