Datasheet

CONTENTS
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Number
Title
Page
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Contents xiii
Part III
Peripheral Module
Chapter 12
DMA Controller Module
12.1 Overview........................................................................................................... 12-1
12.1.1 DMA Module Features ................................................................................. 12-2
12.2 DMA Signal Description .................................................................................. 12-2
12.3 DMA Transfer Overview.................................................................................. 12-4
12.4 DMA Controller Module Programming Model................................................ 12-5
12.4.1 Source Address Registers (SAR0–SAR3) .................................................... 12-7
12.4.2 Destination Address Registers (DAR0–DAR3) ........................................... 12-7
12.4.3 Byte Count Registers (BCR0–BCR3)........................................................... 12-7
12.4.4 DMA Control Registers (DCR0–DCR3)...................................................... 12-8
12.4.5 DMA Status Registers (DSR0–DSR3) ....................................................... 12-10
12.4.6 DMA Interrupt Vector Registers (DIVR0–DIVR3) ................................... 12-11
12.5 DMA Controller Module Functional Description........................................... 12-11
12.5.1 Transfer Requests (Cycle-Steal and Continuous Modes) ........................... 12-12
12.5.2 Data Transfer Modes .................................................................................. 12-12
12.5.2.1 Dual-Address Transfers .......................................................................... 12-12
12.5.2.2 Single-Address Transfers........................................................................ 12-13
12.5.3 Channel Initialization and Startup .............................................................. 12-13
12.5.3.1 Channel Prioritization............................................................................. 12-13
12.5.3.2 Programming the DMA Controller Module ........................................... 12-13
12.5.4 Data Transfer .............................................................................................. 12-14
12.5.4.1 External Request and Acknowledge Operation...................................... 12-14
12.5.4.2 Auto-Alignment...................................................................................... 12-17
12.5.4.3 Bandwidth Control.................................................................................. 12-18
12.5.5 Termination................................................................................................. 12-18
Chapter 13
Timer Module
13.1 Overview........................................................................................................... 13-1
13.1.1 Key Features ................................................................................................. 13-2
13.2 General-Purpose Timer Units ........................................................................... 13-2
13.3 General-Purpose Timer Programming Model .................................................. 13-2
13.3.1 Timer Mode Registers (TMR0/TMR1) ........................................................ 13-3
13.3.2 Timer Reference Registers (TRR0/TRR1) ................................................... 13-4
13.3.3 Timer Capture Registers (TCR0/TCR1)....................................................... 13-4
13.3.4 Timer Counters (TCN0/TCN1) .................................................................... 13-5