Datasheet

4-20 MCF5407 User’s Manual
Cache Operation
Figure 4-7. Data Cache Locking
A:Ways 0 and 1 are filled.
Ways 2 and 3 are
invalid.
B:CACR[DHLCK] is set,
locking ways 0 and 1.
C:When a set in Way 2 is
occupied, the set in way 3
is used for a cacheable
access.
Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3
Invalid (V = 0)
Valid, not modified (V = 1, M = 0)
Valid, modified (V = 1, M = 1)
After reset, the cache is
invalidated, ways 0 and 1
are then written with data
that should not be
deallocated. Ways 0 and 1
can be filled
systematically by using
the INTOUCH instruction.
After CACR[DHLCK] is
set, subsequent cache
accesses go to ways 2
and 3.
S
et 0
S
et 127
While the cache is
locked and after a
position in ways is full,
the set in Way 3 is
updated.
D:Write hits to ways 0
and 1 update cache
lines.
Way 0 Way 1 Way 2 Way 3
While the cache is
locked, ways 0 and 1 ca
n
be updated by write hits.
In this example, memor
y
is configured as
copyback, so updated
cache lines are marked
modified.