Datasheet

Chapter 4. Local Memory 4-23
Cache Registers
4.10.2 Access Control Registers (ACR0–ACR3)
The ACRs, Figure 4-9, assign control attributes, such as cache mode and write protection,
to specified memory regions. ACR0 and ACR1 control data attributes; ACR2 and ACR3
control instruction attributes. Registers are accessed with the MOVEC instruction with the
Rc encodings in Figure 4-9.
For overlapping data regions, ACR0 takes priority; ACR2 takes priority for overlapping
instruction regions. Data transfers to and from these registers are longword transfers. Bits
12–7, 4, 3, 1, and 0 are always read as zeros.
NOTE:
The SIM MBAR region should be mapped as cache-inhibited
through an ACR.
11 IHLCK Instruction cache half-lock.
0 Normal operation. The cache allocates to the lowest invalid way; if all ways are valid, the cache
allocates to the way pointed at by the round-robin counter and then increments this counter
modulo-4.
1 Half cache operation. The cache allocates to the lowest invalid way of ways 2 and 3; if both of
these ways are valid, the cache allocates to way 2 if the high-order bit of the round-robin
counter is zero; otherwise, it allocates way 3 and then increments the round-robin counter
modulo-2. This locks the content of ways 0 and 1. Ways 0 and 1 are still updated on write hits
and may be pushed or cleared by specific cache push/invalidate instructions.
This implementation allows maximum use of the available cache memory and also provides the
flexibility of setting IHLCK before, during, or after the needed allocations occur.
10 IDCM Instruction default cache mode. For normal operations that do not hit in the RAMBARs or ACRs,
this field defines the effective cache mode.
0 Cacheable
1 Cache-inhibited
9 — Reserved, should be cleared.
8 ICINVA Instruction cache invalidate. Invalidation occurs when this bit is written as a 1. Note the caches
are not cleared on power-up or normal reset.
0 No invalidation is performed.
1 Initiate invalidation of instruction cache. The cache controller sequentially clears all V bits.
Subsequent local memory bus accesses stall until invalidation completes, at which point,
ICINVA is cleared automatically without software intervention. For copyback mode, use
CPUSHL before setting ICINVA.
7–0 — Reserved. These bits must be cleared; otherwise, performance may be affected.
Table 4-4. CACR Field Descriptions (Continued)
Bits Name Description