Datasheet

Chapter 4. Local Memory 4-25
Cache Management
The privileged CPUSHL instruction supports cache management by selectively pushing
and invalidating cache lines. The address register used with CPUSHL directly addresses the
cache’s directory array. The CPUSHL instruction flushes a cache line.
The value of CACR[DDPI,IDPI] determines whether CPUSHL invalidates a cache line
after it is pushed. To push the entire cache, implement a software loop to index through all
sets and through each of the four lines within each set
(a total of 512 lines for the data cache
and 1024 lines for the instruction cache). The state of CACR[DEC,IEC] does not affect the
operation of CPUSHL or CACR[DCINVA,ICINVA]. Disabling a cache by setting
CACR[IEC] or CACR[DEC] makes the cache nonoperational without affecting tags, state
information, or contents.
The contents of An used with CPUSHL specify cache row and line indexes. This differs
from the MC68040 where a physical address is specified. Figure 4-11 shows the An format
for the data cache.
Figure 4-11 shows the An format for the instruction cache.
The following code example flushes the entire
data cache:
_cache_disable:
nop
move.w #0x2700,SR ;mask off IRQs
jsr _cache_flush ;flush the cache completely
clr.l d0
movec d0,ACR0 ;ACR0 off
movec d0,ACR1 ;ACR1 off
move.l #0x01000000,d0 ;Invalidate and disable cache
movec d0,CACR
rts
_cache_flush:
nop ;synchronize—flush store buffer
moveq.l #0,d0 ;initialize way counter
moveq.l #0,d1 ;initialize set counter
move.l d0,a0 ;initialize cpushl pointer
setloop:
cpushl dc,(a0) ;push cache line a0
add.l #0x0010,a0 ;increment set index by 1
addq.l #1,d1 ;increment set counter
cmpi.l #128,d1 ;are sets for this way done?
bne setloop
moveq.l #0,d1 ;set counter to zero again
31 11 10 4 3 0
0 Set Index Line Index
Figure 4-10. An Format (Data Cache)
31 12 11 4 3 0
0 Set Index Line Index
Figure 4-11. An Format (Instruction Cache)