Datasheet

4-26 MCF5407 User’s Manual
Cache Management
addq.l #1,d0 ;increment to next way
move.l d0,a0 ;set = 0, way = d0
cmpi.l #4,d0 ;flushed all the ways?
bne setloop
rts
The following CACR loads assume the instruction cache has been invalidated, the default
instruction cache mode is cacheable, and the default data cache mode is copyback.
dataCacheLoadAndLock:
move.l #0xa3080800,d0; enable and invalidate data cache ...
movec d0,cacr ; ... in the CACR
The following code preloads half of the data cache (4 Kbytes). It assumes a contiguous
block of data is to be mapped into the data cache, starting at a 0-modulo-4K address.
move.l #256,d0 ;256 16-byte lines in 4K space
lea data_,a0 ; load pointer defining data area
dataCacheLoop:
tst.b (a0) ;touch location + load into data cache
lea 16(a0),a0 ;increment address to next line
subq.l #1,d0 ;decrement loop counter
bne.b dataCacheLoop ;if done, then exit, else continue
; A 4K region has been loaded into levels 0 and 1 of the 8K data cache. lock it!
move.l #0xaa088000,d0 ;set the data cache lock bit ...
movec d0,cacr ; ... in the CACR
rts
align 16
The following CACR loads assume the data cache has been invalidated, the default
instruction cache mode is cacheable and the default operand cache mode is copyback.
Note that this function must be mapped into a cache inhibited or SRAM space or these text
lines will be prefetched into the instruction cache, which may displace some of the 8-Kbyte
space being explicitly fetched.
instructionCacheLoadAndLock:
move.l #0xa2088100,d0 ;enable and invalidate the instruction
movec d0,cacr ;cache in the CACR
The following code segments preload half of the instruction cache (8 Kbytes). It assumes a
contiguous block of data is to be mapped, starting at a 0-modulo-8K address
move.l #512,d0 ;512 16-byte lines in 8K space
lea code_,a0 ;load pointer defining code area
instCacheLoop:
; intouch (a0) ;touch location + load into instruction cache
; Note in the assembler we use, there is no INTOUCH opcode. The following
; is used to produce the required binary representation
cpushl #nc,(a0) ;touch location + load into