Datasheet

4-28 MCF5407 User’s Manual
Cache Operation Summary
4.12.2 Data Cache State Transitions
Using the V and M bits, the data cache supports a line-based protocol allowing individual
cache lines to be invalid, valid, or modified. To maintain memory coherency, the data cache
supports both write-through and copyback modes, specified by the corresponding
ACR[CM], or CACR[DDCM] if no ACR matches.
Read or write misses to copyback regions cause the cache controller to read a cache line
from memory into the cache. If available, tag and data from memory update an invalid line
in the selected set. The line state then changes from invalid to valid by setting the V bit. If
all lines in the row are already valid or modified, the pseudo-round-robin replacement
algorithm selects one of the four lines and replaces the tag and data. Before replacement,
modified lines are temporarily buffered and later copied back to memory after the new line
has been read from memory.
Figure 4-13 shows the three possible data cache line states and possible processor-initiated
transitions for memory configured as copyback. Transitions are labeled with a capital letter
indicating the previous state and a number indicating the specific case listed in Table 4-7.
Figure 4-13. Data Cache Line State Diagram—Copyback Mode
Cache
invalidate
II5 No action;
stay in invalid state.
IV5 No action;
go to invalid state.
Cache
push
II6,
II7
No action;
stay in invalid state.
IV6 No action;
go to invalid state.
IV7 No action;
stay in valid state.
Table 4-6. Instruction Cache Line State Transitions (Continued)
Access
Current State
Invalid (V = 0) Valid (V = 1)
Invalid
CD1—CPU
CI3—CPU
Valid
V = 1
Modified
read miss
write miss
CI5—DCINVA
CI6—CPUSHL & DDPI
CI7—CPUSHL & DDPI
CV1—CPU read miss
CV2—CPU read hit
CV7—CPUSHL & DDPI
CD2—CPU read hit
CD3—CPU write miss
CD4—CPU write hit
CD5—DCINVA
CD6—CPUSHL & DDPI
CV3—CPU write miss
CV4—CPU write hit
CI1—CPU read miss
CV5—DCINVA
CV6—CPUSHL & DDPI
V = 0
M = 0
V = 1
M = 1
CD7—CPUSHL
& DDPI