Datasheet

Chapter 4. Local Memory 4-29
Cache Operation Summary
Figure 4-14 shows the two possible states for a cache line in write-through mode.
Figure 4-14. Data Cache Line State Diagram—Write-Through Mode
Table 4-7 describes data cache line transitions and the accesses that cause them.
Table 4-7. Data Cache Line State Transitions
Access
Current State
Invalid (V = 0) Valid (V = 1, M = 0) Modified (V = 1, M = 1)
Read
miss
(C,W)I1 Read line from
memory and update
cache;
supply data to
processor;
go to valid state.
(C,W)V1 Read new line from
memory and update
cache;
supply data to processor;
stay in valid state.
CD1 Push modified line to
buffer;
read new line from memory
and update cache;
supply data to processor;
write push buffer contents
to memory;
go to valid state.
Read hit (C,W)I2 Not possible. (C,W)V2 Supply data to processor;
stay in valid state.
CD2 Supply data to processor;
stay in modified state.
Write
miss
(copy-
back)
CI3 Read line from
memory and update
cache;
write data to cache;
go to modified state.
CV3 Read new line from
memory and update
cache;
write data to cache;
go to modified state.
CD3 Push modified line to
buffer;
read new line from memory
and update cache;
write push buffer contents
to memory;
stay in modified state.
Write
miss
(write-
through)
WI3 Write data to
memory;
stay in invalid state.
WV3 Write data to memory;
stay in valid state.
WD3 Write data to memory;
stay in modified state.
Cache mode changed for
the region corresponding to
this line. To avoid this state,
execute a CPUSHL
instruction or set
CACR[DCINVA,ICINVA]
before switching modes.
Write hit
(copy-
back)
CI4 Not possible. CV4 Write data to cache;
go to modified state.
CD4 Write data to cache;
stay in modified state.
WI1—CPU read miss
Invalid Valid
WI3—CPU write miss
WI5—DCINVA
WI6—CPUSHL & DDPI
WI7—CPUSHL & DDPI
WV1—CPU read miss
WV2—CPU read hit
WV3—CPU write miss
WV4—CPU write hit
WV7—CPUSHL & DDPI
WV5—DCINVA
WV6—CPUSHL & DDPI
V = 0 V = 1