Datasheet

Chapter 4. Local Memory 4-31
Cache Operation Summary
In Table 4-10 the current state is modified.
Table 4-9. Data Cache Line State Transitions (Current State Valid)
Access Response
Read miss (C,W)V1 Read new line from memory and update cache;
supply data to processor; stay in valid state.
Read hit (C,W)V2 Supply data to processor;
stay in valid state.
Write miss (copyback) CV3 Read new line from memory and update cache;
write data to cache;
go to modified state.
Write miss (write-through) WV3 Write data to memory;
stay in valid state.
Write hit (copyback) CV4 Write data to cache;
go to modified state.
Write hit (write-through) WV4 Write data to memory and to cache;
stay in valid state.
Cache invalidate (C,W)V5 No action;
go to invalid state.
Cache push (C,W)V6 No action;
go to invalid state.
Cache push (C,W)V7 No action;
stay in valid state.
Table 4-10. Data Cache Line State Transitions (Current State Modified)
Access Response
Read miss CD1 Push modified line to buffer;
read new line from memory and update cache;
supply data to processor;
write push buffer contents to memory;
go to valid state.
Read hit CD2 Supply data to processor;
stay in modified state.
Write miss
(copyback)
CD3 Push modified line to buffer;
read new line from memory and update cache;
write push buffer contents to memory;
stay in modified state.
Write miss
(write-through)
WD3 Write data to memory;
stay in modified state.
Cache mode changed for the region corresponding to this line. To avoid this state,
execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
Write hit
(copyback)
CD4 Write data to cache;
stay in modified state.
Write hit
(write-through)
WD4 Write data to memory and to cache;
go to valid state.
Cache mode changed for the region corresponding to this line. To avoid this state,
execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.