Datasheet

5-2 MCF5407 User’s Manual
Signal Descriptions
The Version 2 ColdFire core implemented the original debug architecture, now called
Revision A. Based on feedback from customers and third-party developers, enhancements
have been added to succeeding generations of ColdFire cores. The Version 3 core
implements the Revision B of the debug architecture, providing more flexibility for
configuring the hardware breakpoint trigger registers and removing the restrictions
involving concurrent BDM processing while hardware breakpoint registers are active.
The MCF5407 core implements Revision C of the debug architecture, which more than
doubles the on-chip breakpoint registers and provides an ability to interrupt debug service
routines. For Revision C, the revision level bit, CSR[HRL], is 2. See Section 5.4.4,
“Configuration/Status Register (CSR).”
5.2 Signal Descriptions
Table 5-1 describes debug module signals. All ColdFire debug signals are unidirectional
and related to a rising edge of the processor core’s clock signal. The standard 26-pin debug
connector is shown in Section 5.7, “Motorola-Recommended BDM Pinout.”
Table 5-1. Debug Module Signals
Signal Description
Development Serial
Clock (DSCLK)
Internally synchronized input that clocks the serial communication port to the debug module.
Maximum frequency is 1/5 the processor CLK speed. At the synchronized rising edge of
DSCLK, the data input on DSI is sampled and DSO changes state. The logic level on DSCLK is
validated if it has the same value on two consecutive rising CLKIN edges.
Development Serial
Input (DSI)
Internally synchronized input that provides data input for the serial communication port to the
debug module.
Development Serial
Output (DSO)
Provides serial output communication for debug module responses. DSO is registered
internally.
Breakpoint (BKPT
) Used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted state
after the current instruction completes. Halt status is reflected on processor status/debug data
signals (PSTDDATA[7:0]) as the value 0xF. If CSR[BKD] is set (disabling normal BKPT
functionality), asserting BKPT
generates a debug interrupt exception in the processor.
Processor Status
Clock (PSTCLK)
Half-speed version of the processor clock. Its rising edge appears in the center of the two
processor-cycle window of valid PSTDDATA output. See Figure 5-2. Because debug trace port
signals change on alternate processor cycles and are unrelated to external bus frequency,
PSTCLK helps the development system sample PSTDDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK and PSTDDATA outputs from
toggling without disabling triggers. Non-quiescent operation can be reenabled by clearing
CSR[PCD], although the emulator must resynchronize with the PSTDDATA output.
PSTCLK starts clocking only when the first non-zero PST value (0xC, 0xD, or 0xF) occurs
during system reset exception processing. Table 5-4 describes PST values. Chapter 7,
“Phase-Locked Loop (PLL),” describes PSTCLK generation.
Processor
Status/Debug Data
(PSTDDATA[7:0])
These outputs indicate both processor status and captured address and data values and are
discussed more thoroughly in Section 5.2.1, “Processor Status/Debug Data (PSTDDATA[7:0]).