Datasheet

Chapter 5. Debug Support 5-5
Real-Time Trace Support
Execution speed is affected only when three storage elements have valid data to be dumped
to the PSTDDATA port. This occurs only when two values are captured simultaneously in
a read-modify-write operation; the core stalls until two FIFO entries are available.
Table 5-4 shows the encoding of these signals.
Table 5-4. Processor Status Encoding
PST[3:0]
Definition
Hex Binary
0x0 0000 Continue execution. Many instructions execute in one processor cycle. If an instruction requires more
clock cycles, subsequent clock cycles are indicated by driving PSTDDATA outputs with this encoding.
0x1 0001 Begin execution of one instruction. For most instructions, this encoding signals the first clock cycle of
an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions,
generate different encodings.
0x2 0010 Begin execution of two instructions. For superscalar instruction dispatches, this encoding signals the
first clock cycle of the simultaneous instructions’ execution.
0x3 0011 Entry into user-mode. Signaled after execution of the instruction that caused the MCF5407 to enter
user mode.
0x4 0100 Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug
and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword)
directly to the PSTDDATA port, independent of debug module configuration. When WDDATA is
executed, a value of 0x4 is signaled, followed by the appropriate marker, and then the data transfer on
the PSTDDATA port. Transfer length depends on the WDDATA operand size.
0x5 0101 Begin execution of taken branch. For some opcodes, a branch target address may be displayed on
PSTDDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
indicated by the PST marker value preceding the DDATA nibble that begins the data output. See
Section 5.3.1, “Begin Execution of Taken Branch (PST = 0x5).”
0x6 0110 Begin execution of instruction plus a taken branch. The processor completes execution of a taken
conditional branch instruction and simultaneously starts executing the target instruction. This is
achieved through branch folding.
0x7 0111 Begin execution of return from exception (RTE) instruction.
0x8–
0xB
1000–
1011
Indicates the size of the next consecutive nibbles. The encoding is driven onto the PSTDDATA port one
clock cycle before the data is displayed on PSTDDATA.
0x8 Begin 1-byte transfer on PSTDDATA.
0x9 Begin 2-byte transfer on PSTDDATA.
0xA Begin 3-byte transfer on PSTDDATA.
0xB Begin 4-byte transfer on PSTDDATA.
0xC 1100 Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace)
generate a different encoding, 0xD. Because the 0xC encoding defines a multiple-cycle mode,
PSTDDATA outputs are driven with 0xC until exception processing completes.
0xD 1101 Entry into emulator mode.
Displayed during emulation mode (debug interrupt or optionally trace).
Because this encoding defines a multiple-cycle mode, PSTDDATA outputs are driven with 0xD until
exception processing completes.
0xE 1110 A breakpoint state change causes this encoding to assert for one cycle only followed by the trigger
status value. If the processor stops waiting for an interrupt, the encoding is asserted for multiple cycles.
See Section 5.3.2, “Processor Stopped or Breakpoint State Change (PST = 0xE).”
0xF 1111 Processor is halted. See Section 5.3.3, “Processor Halted (PST = 0xF).”