Datasheet

Chapter 5. Debug Support 5-9
Programming Model
Figure 5-5. Debug Programming Model
These registers are accessed through the BDM port by new BDM commands, WDMREG and
RDMREG, described in Section 5.5.3.3, “Command Set Descriptions.” These commands
contain a 5-bit field, DRc, that specifies the register, as shown in Table 5-6.
Table 5-6. BDM/Breakpoint Registers
DRc[4–0] Register Name Abbreviation Initial State Page
0x00 Configuration/status register CSR 0x0020_0000 p. 5-13
0x01–0x04 Reserved — — —
0x05 BDM address attribute register BAAR 0x0000_0005 p. 5-12
0x06 Address attribute trigger register AATR 0x0000_0005 p. 5-10
ABLR1
ABHR1
AATR1
PC breakpoint 1 register
PC breakpoint 3 register
PC breakpoint mask register
PC breakpoint register
Data breakpoint register
Data breakpoint mask register
Data breakpoint 1 register
Data breakpoint mask 1 register
Trigger definition register
Extended trigger definition registerXTDR
Configuration/status register
BDM address attribute register
PC breakpoint 2 register
Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care).
All debug control registers are writable from the external development system or the CPU via the
WDEBUG instruction.
CSR is write-only from the programming model as debug control register 0x00 using the supervisor-mode
WDEBUG instruction. It can be read from and written through the BDM port using the
RDMREG and
WDMREG commands.
Address attribute trigger register
Address low breakpoint register
Address high breakpoint register
Address 1 attribute register
Address low breakpoint 1 register
Address high breakpoint 1 register
31 15 7 0
31 15 7 0
31 15 7 0
31 15 0
31 15 0
31 15 0
31 15 0
31 15
31 15 0
31 15 0
31 15 0
31 15 0
31 15 0
31 15 0
AATR
ABLR
ABHR
BAAR
CSR
DBR
DBMR
PBR
DBR1
DBMR1
PBR1
PBR2
PBR3
PBMR
TDR