Datasheet

5-12 MCF5407 User’s Manual
Programming Model
5.4.2 Address Breakpoint Registers (ABLR/ABLR1,
ABHR/ABHR1)
The address breakpoint low and high registers (ABLR, ABLR1, ABHR, and ABHR1),
Figure 5-7, define regions in the processor’s data address space that can be used as part of
the trigger. These register values are compared with the address for each transfer on the
processor’s high-speed local bus. TDR determines if the trigger is in the address in ABLR
or either inside or outside of the range bound by ABLR and ABHR. XTDR determines the
same for ABLR1 and ABHR1.
Table 5-8 describes ABLR and ABLR1 fields.
Table 5-9 describes ABHR and ABHR1 fields.
5.4.3 BDM Address Attribute Register (BAAR)
The BAAR defines the address space for memory-referencing BDM commands. See
Figure 5-8. The reset value of 0x5 sets supervisor data as the default address space.
31 0
Field Address
Reset —
R/W ABHR and ABHR1 are accessible in supervisor mode as debug control registers 0x0C and 0x1C, using the
WDEBUG instruction and via the BDM port using the
RDMREG and WDMREG commands.
ABLR and ABLR1 are accessible in supervisor mode as debug control register 0x0D and 0x1D, using the
WDEBUG instruction and via the BDM port using the
WDMREG command.
DRc[4–0] 0x0D (ABLR); 0x1D (ABLR1); 0x0C (ABHR); 0x1C (ABHR1)
Figure 5-7. Address Breakpoint Registers (ABLR, ABHR, ABLR1, ABHR1)
Table 5-8. ABLR and ABLR1 Field Description
Bits Name Description
31–0 Address Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range.
Breakpoints for specific addresses are programmed into ABLR or ABLR1.
Table 5-9. ABHR and ABHR1 Field Description
Bits Name Description
31–0 Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.