Datasheet

5-14 MCF5407 User’s Manual
Programming Model
Table 5-11 describes CSR fields.
Table 5-11. CSR Field Descriptions
Bit Name Description
31–28 BSTAT Breakpoint status. Provides read-only status information concerning hardware breakpoints. Also
output on PSTDDATA when it is not displaying PST or other processor data. BSTAT is cleared by a
TDR or XTDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1
breakpoint is triggered and the level-2 breakpoint is disabled.
0000 No breakpoints enabled
0001 Waiting for level-1 breakpoint
0010 Level-1 breakpoint triggered
0101 Waiting for level-2 breakpoint
0110 Level-2 breakpoint triggered
27 FOF Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM.
26 TRG Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor core and
forced entry into BDM. Reset and the debug
GO command clear TRG.
25 HALT Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM. Reset
and the debug
GO command reset HALT.
24 BKPT Breakpoint assert. If BKPT is set, BKPT
was asserted, forcing the processor into BDM. Reset and
the debug
GO command clears this bit.
23–20 HRL Hardware revision level. Indicates the level of debug module functionality. An emulator could use
this information to identify the level of functionality supported.
0000 Initial debug functionality (Revision A)
0001 Revision B
0010 Revision C (this is the only valid value for the MCF5407)
19 — Reserved, should be cleared.
18 BKD Breakpoint disable. Used to disable the normal BKPT
input functionality and to allow the assertion
of BKPT
to generate a debug interrupt.
0 Normal operation
1 BKPT
is edge-sensitive: a high-to-low edge on BKPT signals a debug interrupt to the processor.
The processor makes this interrupt request pending until the next sample point, when the
exception is initiated. In the ColdFire architecture, the interrupt sample point occurs once per
instruction. There is no support for nesting debug interrupts.
17 PCD PSTCLK disable. Setting PCD disables generation of PSTCLK and PSTDDATA outputs and forces
them to remain quiescent.
16 IPW Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s
programming model registers. IPW can be modified only by commands from the external
development system.
15 MAP Force processor references in emulator mode.
0 All emulator-mode references are mapped into supervisor code and data spaces.
1 The processor maps all references while in emulator mode to a special address space, TT = 10,
TM = 101 or 110.
14 TRC Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode when a
trace exception occurs.
13 EMU Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See
Section 5.6.1.1, “Emulator Mode.”