Datasheet

5-18 MCF5407 User’s Manual
Programming Model
5.4.7 Trigger Definition Register (TDR)
The TDR, shown in Table 5-13, configures the operation of the hardware breakpoint logic
that corresponds with the ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and
DBR/DBMR registers within the debug module. In conjunction with the XTDR and its
associated debug registers, TDR controls the actions taken under the defined conditions.
Breakpoint logic may be configured as one- or two-level triggers. TDR[31–16] and/or
XTDR[31–16] define second-level triggers and bits 15–0 define first-level triggers.
NOTE:
The debug module has no hardware interlocks, so to prevent
spurious breakpoint triggers while the breakpoint registers are
being loaded, disable TDR and XTDR (by clearing
TDR[29,13] and XTDR[29,13]) before defining triggers.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
Section 5.4.9, “Resulting Set of Possible Trigger Combinations,” describes how to handle
multiple breakpoint conditions.
Table 5-17 describes TDR fields.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field TRC EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI EAI EAR EAL EPC PCI
Reset 0000_0000_0000_0000
R/W Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the
BDM port using the
WDMREG command.
151413 12 11 10 9 8 7 6 543210
Field — EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI EAI EAR EAL EPC PCI
Reset 0000_0000_0000_0000
R/W Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the
BDM port using the
WDMREG command.
DRc[4–0] 0x07
Figure 5-13. Trigger Definition Register (TDR)
Second-Level Triggers
First-Level Triggers