Datasheet

Chapter 5. Debug Support 5-19
Programming Model
5.4.8 Extended Trigger Definition Register (XTDR)
The XTDR configures the operation of the hardware breakpoint logic that corresponds with
the ABHR1/ABLR1/AATR1 and DBR1/DBMR1 registers within the debug module and,
in conjunction with the TDR and its associated debug registers, controls the actions taken
under the defined conditions. The breakpoint logic may be configured as a one- or two-level
trigger, where TDR[31–16] and/or XTDR[31–16] define the second-level trigger and bits
15–0 define the first-level trigger. The XTDR is accessible in supervisor mode as debug
control register 0x17 using the WDEBUG instruction and via the BDM port using the
WDMREG command.
Table 5-17. TDR Field Descriptions
Bits Name Description
31–30 TRC Trigger response control. Determines how the processor responds to a completed trigger condition.
The trigger response is always displayed on PSTDDATA.
00 Display on PSTDDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
29/13 EBL Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] or XTDR[EBL]
enables a breakpoint trigger; clearing both disables all breakpoints.
28–22
12–6
EDx Setting an EDx bit enables the corresponding data breakpoint condition based on the size and
placement on the processor’s local data bus. Clearing all EDx bits disables data breakpoints.
28/12 EDLW Data longword. Entire processor’s local data bus.
27/11 EDWL Lower data word.
26/10 EDWU Upper data word.
25/9 EDLL Lower lower data byte. Low-order byte of the low-order word.
24/8 EDLM Lower middle data byte. High-order byte of the low-order word.
23/7 EDUM Upper middle data byte. Low-order byte of the high-order word.
22/6 EDUU Upper upper data byte. High-order byte of the high-order word.
21/5 DI Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the
DBR contents.
20–18/
4–2
EAx Enable address bits. Setting an EA bit enables the corresponding address breakpoint. Clearing all
three bits disables the breakpoint.
20/4 EAI Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR
and ABHR.
19/3 EAR Enable address breakpoint range. The breakpoint is based on the inclusive range defined
by ABLR and ABHR.
18/2 EAL Enable address breakpoint low. The breakpoint is based on the address in the ABLR.
17/1 EPC Enable PC breakpoint. If set, this bit enables the PC breakpoint.
16/0 PCI Breakpoint invert. If set, this bit allows execution outside a given region as defined by
PBR/PBR1/PBR2/PBR3 and PBMR to enable a trigger. If cleared, the PC breakpoint is defined
within the region defined by PBR/PBR1/PBR2/PBR3 and PBMR.