Datasheet

5-22 MCF5407 User’s Manual
Background Debug Mode (BDM)
then if (PC_breakpoint)
if (Address_breakpoint {&& Data_breakpoint})
then if (PC_breakpoint
|| Address1_breakpoint{&& Data1_breakpoint})
if (Address1_breakpoint {&& Data1_breakpoint})
then if (PC_breakpoint
|| Address_breakpoint{&& Data_breakpoint})
In this example, PC_breakpoint is the logical summation of the PBR/PBMR, PBR1, PBR2,
and PBR3 breakpoint registers; Address_breakpoint is a function of ABHR, ABLR, and
AATR; Data_breakpoint is a function of DBR and DBMR; Address1_breakpoint is a
function of ABHR1, ABLR1, and AATR1; and Data1_breakpoint is a function of DBR1
and DBMR1. In all cases, the data breakpoints can be included with an address breakpoint
to further qualify a trigger event as an option.
5.5 Background Debug Mode (BDM)
The ColdFire Family implements a low-level system debugger in the microprocessor
hardware. Communication with the development system is handled through a dedicated,
high-speed serial command interface. The ColdFire architecture implements the BDM
controller in a dedicated hardware module. Although some BDM operations, such as CPU
register accesses, require the CPU to be halted, other BDM commands, such as memory
accesses, can be executed while the processor is running.
5.5.1 CPU Halt
Although many BDM operations can occur in parallel with CPU operations, unrestricted
BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt
are listed below in order of priority:
1. A catastrophic fault-on-fault condition automatically halts the processor.
2. A hardware breakpoint can be configured to generate a pending halt condition
similar to the assertion of BKPT
. This type of halt is always first made pending in
the processor. Next, the processor samples for pending halt and interrupt conditions
once per instruction. When a pending condition is asserted, the processor halts
execution at the next sample point. See Section 5.6.1, “Theory of Operation.”
3. The execution of a HALT instruction immediately suspends execution. Attempting
to execute HALT in user mode while CSR[UHE] = 0 generates a privilege violation
exception. If CSR[UHE] = 1, HALT can be executed in user mode. After HALT
executes, the processor can be restarted by serial shifting a
GO command into the
debug module. Execution continues at the instruction after HALT.