Datasheet

xviii MCF5407 User’s Manual
CONTENTS
Paragraph
Number
Title
Page
Number
18.4.7.4 Transfers Using Mixed Port Sizes .......................................................... 18-15
18.5 Misaligned Operands ...................................................................................... 18-16
18.6 Bus Errors ....................................................................................................... 18-17
18.7 Interrupt Exceptions........................................................................................ 18-17
18.7.1 Level 7 Interrupts........................................................................................ 18-18
18.7.2 Interrupt-Acknowledge Cycle..................................................................... 18-19
18.8 Bus Arbitration................................................................................................ 18-20
18.8.1 Bus Arbitration Signals............................................................................... 18-21
18.9 General Operation of External Master Transfers............................................ 18-21
18.9.1 Two-Device Bus Arbitration Protocol (Two-Wire Mode) ......................... 18-25
18.9.2 Multiple External Bus Device Arbitration Protocol (Three-Wire Mode)... 18-29
18.10 Reset Operation............................................................................................... 18-33
18.10.1 Master Reset ............................................................................................... 18-34
18.10.2 Software Watchdog Reset........................................................................... 18-35
Chapter 19
IEEE 1149.1 Test Access Port (JTAG)
19.1 Overview........................................................................................................... 19-1
19.2 JTAG Signal Descriptions ............................................................................... 19-2
19.3 TAP Controller.................................................................................................. 19-3
19.4 JTAG Register Descriptions ............................................................................. 19-4
19.4.1 JTAG Instruction Shift Register .................................................................. 19-5
19.4.2 IDCODE Register ......................................................................................... 19-6
19.4.3 JTAG Boundary-Scan Register .................................................................... 19-7
19.4.4 JTAG Bypass Register................................................................................ 19-10
19.5 Restrictions ..................................................................................................... 19-10
19.6 Disabling IEEE Standard 1149.1 Operation ................................................... 19-10
19.7 Obtaining the IEEE Standard 1149.1.............................................................. 19-11
Chapter 20
Electrical Specifications
20.1 General Parameters ........................................................................................... 20-1
20.1.1 Supply Voltage Sequencing and Separation Cautions.................................. 20-3
20.2 Clock Timing Specifications............................................................................. 20-4
20.3 Input/Output AC Timing Specifications........................................................... 20-6
20.4 Reset Timing Specifications ........................................................................... 20-15
20.5 Debug AC Timing Specifications................................................................... 20-16
20.6 Timer Module AC Timing Specifications ...................................................... 20-17
20.7 I
2
C Input/Output Timing Specifications......................................................... 20-18
20.8 UART Module AC Timing Specifications ..................................................... 20-19