Datasheet

CONTENTS
Paragraph
Number
Title
Page
Number
Contents xix
20.9 Parallel Port (General-Purpose I/O) Timing Specifications ........................... 20-22
20.10 DMA Timing Specifications........................................................................... 20-23
20.11 IEEE 1149.1 (JTAG) AC Timing Specifications ........................................... 20-24
Appendix A
Migrating from the ColdFire MCF5307 to the MCF5407
A.1 Overview............................................................................................................ A-1
A.2 Instruction Set Additions ................................................................................... A-2
A.3 Enhanced Memories........................................................................................... A-3
A.4 On-Chip DMA Modifications............................................................................ A-4
A.5 UART Enhancements ........................................................................................ A-5
A.6 Timing Differences ............................................................................................ A-6
A.6.1 Phase-Locked Loop (PLL)............................................................................. A-6
A.6.2 Timing Relationships..................................................................................... A-7
A.7 Reset Initialization Modifications...................................................................... A-8
A.8 Revision C Debug ............................................................................................ A-10
A.8.1 Debug Interrupts and Interrupt Requests
in Emulator Mode .................................................................................... A-10
A.8.2 On-Chip Breakpoint Registers..................................................................... A-12
A.8.2.1 Write Debug Module Register (wdmreg) ................................................ A-12
A.8.3 Debug Programming Model ........................................................................ A-14
A.8.3.1 Address Breakpoint 1 Registers (ABLR1, ABHR1) ............................... A-14
A.8.3.2 Address Attribute Breakpoint Register 1 (AATR1) ................................ A-14
A.8.3.3 Program Counter Breakpoint Registers 1–3 (PBR1–PBR3) ................... A-14
A.8.3.4 Data Breakpoint Register 1 (DBR1, DBMR1) ........................................ A-15
A.8.3.5 Extended Trigger Definition Register (XTDR) ....................................... A-15
A.8.4 Debug Interrupt Exception Vectors ............................................................. A-15
A.8.5 Processor Status and Debug Data Output Signals ....................................... A-16
A.8.6 Debug C Summary....................................................................................... A-17
A.9 Voltage Input Changes..................................................................................... A-17
A.10 PLL Power Supply Filter Circuit ..................................................................... A-18
A.11 Pin-Assignment Compatibility......................................................................... A-18
Appendix B
List of Memory Maps