Datasheet

Chapter 6. SIM Overview 6-1
Chapter 6
SIM Overview
This chapter provides detailed operation information regarding the system integration
module (SIM). It describes the SIM programming model, bus arbitration, and
system-protection functions for the MCF5407.
6.1 Features
The SIM, shown in Figure 6-1, provides overall control of the bus and serves as the
interface between the ColdFire core processor complex and the internal peripheral devices.
Figure 6-1. SIM Block Diagram
DRAM Controller External
Bus Interface
SYSTEM INTEGRATION MODULE (SIM)
32-Bit Address Bus
32-Bit Data Bus
Interrupt Controller
PLL
CLKIN
RSTI
RSTO
PCLK
Xn
CS[7:0]
888
8
10 ICRs
MBAR
IMR
CSARs CSCRs CSMRs
IRQ[1,3,5,7]
4
DRAM Controller Outputs
AVR
IPR
IRQPAR
SWIVR
SWSR SYPCR
RSR
System Control PLL Control
PLL
Base Address
MPARK
Bus Master Park
DMR0/1DACR0/1
Addr/Cntrl Mask
DRAM Control
DCR
Parallel Port
PA R
Software
Watchdog
Two
Two UARTs
DMA
I
2
C Module
Four
Channels
General-
Purpose
Timers
V4 COLDFIRE PROCESSOR COMPLEX
CLKIN (to on-chip peripherals)
Control Signals
Chip Select Module