Datasheet

Chapter 6. SIM Overview 6-3
Programming Model
6.2 Programming Model
The following sections describe the registers incorporated into the SIM.
6.2.1 SIM Register Memory Map
Table 6-1 shows the memory map for the SIM registers. The internal registers in the SIM
are memory-mapped registers offset from the MBAR address pointer defined in
MBAR[BA]. This supervisor-level register is described in Section 6.2.2, “Module Base
Address Register (MBAR).” Because SIM registers depend on the base address defined in
MBAR[BA], MBAR must be programmed before SIM registers can be accessed.
NOTE:
Although external masters cannot access the MCF5407’s
on-chip memories or MBAR, they can access any of the SIM
memory map and peripheral registers, such as those belonging
to the interrupt controller, chip-select module, UARTs, timers,
DMA, and I
2
C.
Table 6-1. SIM Registers
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x000 Reset status register
(RSR) [p. 6-5]
System protection
control register
(SYPCR) [p. 6-8]
Software watchdog
interrupt vector register
(SWIVR) [p. 6-9]
Software watchdog
service register (SWSR)
[p. 6-9]
0x004 Pin assignment register (PAR) [p. 6-10] Interrupt port
assignment register
(IRQPAR) [p. 9-7]
Reserved
0x008 PLL control (PLLCR)
[p. 7-3]
Reserved
0x00C Default bus master park
register (MPARK)
[p. 6-11]
Reserved
0x010–
0x03C
Reserved
Interrupt Controller Registers [p. 9-2]
0x040 Interrupt pending register (IPR) [p. 9-6]
0x044 Interrupt mask register (IMR) [p. 9-6]
0x048 Reserved Autovector register
(AVR) [p. 9-5]
Interrupt Control Registers (ICRs) [p. 9-3]