Datasheet

6-4 MCF5407 User’s Manual
Programming Model
6.2.2 Module Base Address Register (MBAR)
The supervisor-level MBAR, Figure 6-2, specifies the base address and allowable access
types for all internal peripherals. It is written with a MOVEC instruction using the CPU
address 0xC0F. (See the ColdFire Family Programmer’s Reference Manual.) MBAR can
be read or written through the debug module as a read/write register, as described in
Chapter 5, “Debug Support.” Only the debug module can read MBAR.
The valid bit, MBAR[V], is cleared at system reset to prevent incorrect references before
MBAR is written; other MBAR bits are uninitialized at reset. To access internal peripherals,
write MBAR with the appropriate base address (BA) and set MBAR[V] after system reset.
All internal peripheral registers occupy a single relocatable memory block along 4-Kbyte
boundaries. If MBAR[V] is set, MBAR[BA] is compared to the upper 20 bits of the full
32-bit internal address to determine if an internal peripheral is being accessed. MBAR
masks specific address spaces using the address space fields. Attempts to access a masked
address space generate an external bus access.
Addresses hitting overlapping memory spaces take the following priority:
1. MBAR
2. SRAM and caches
3. Chip select
NOTE:
The MBAR region must be mapped to non-cacheable space.
0x04C Software watchdog
timer (ICR0) [p. 9-3]
Timer0 (ICR1) [p. 9-3] Timer1 (ICR2) [p. 9-3] I
2
C (ICR3) [p. 9-3]
0x050 UART0 (ICR4) [p. 9-3] UART1 (ICR5) [p. 9-3] DMA0 (ICR6) [p. 9-3] DMA1 (ICR7) [p. 9-3]
0x054 DMA2 (ICR8) [p. 9-3] DMA3 (ICR9) [p. 9-3] Reserved
31 12 11 10 9 8 7 6 5 4 3 2 1 0
Field BA — WP — AM C/I SC SD UC UD V
Reset Undefined 0
R/W W (supervisor only); R/W through debug module (only the debug module can read MBAR)
Address CPU + 0x0C0F
Figure 6-2. Module Base Address Register (MBAR)
Table 6-1. SIM Registers (Continued)
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
A
ttr
ib
ute
M
as
k
Bi
ts