Datasheet

Chapter 6. SIM Overview 6-5
Programming Model
Table 6-2 describes MBAR fields.
The following example shows how to set the MBAR to location 0x1000_0000 using the D0
register. Setting MBAR[V] validates the MBAR location. This example assumes all
accesses are valid:
move.1 #0x10000001,DO
movec DO,MBAR
6.2.3 Reset Status Register (RSR)
The reset status register (RSR), Figure 6-3, contains two status bits, HRST and SWTR.
Reset control logic sets one of the bits depending on whether the last reset was caused by
an external device asserting RSTI
(HRST = 1) or by the software watchdog timer
(SWTR = 1). Only one RSR bit can be set at any time. If a reset occurs, reset control logic
sets only the bit that indicates the cause of reset.
Table 6-2. MBAR Field Descriptions
Bits Field Description
31–12 BA Base address. Defines the base address for a 4-Kbyte address range.
11–9 — Reserved, should be cleared.
8 WP Write protect. Mask bit for write cycles in the MBAR-mapped register address range.
0 Module address range is read/write.
1 Module address range is read only.
7 — Reserved, should be cleared.
6 AM Alternate master mask. When AM = 0 and an alternate master (external master or DMA) accesses
MBAR-mapped registers, MBAR[SC,SD,UC,UD] are ignored in address decoding. These fields
mask address space, placing the MBAR-mapped register in a specific address space or spaces.
5 C/I Mask CPU space and interrupt acknowledge cycles.
0 Activates the corresponding MBAR-mapped register
1 Regular external bus access
4 SC Setting masks supervisor code space in MBAR address range
3 SD Setting masks supervisor data space in MBAR address range
2 UC Setting masks user code space in MBAR address range
1 UD Setting masks user data space in MBAR address range
0 V Valid. Determines whether MBAR settings are valid.
0 MBAR contents are invalid.
1 MBAR contents are valid.
7654 0
Field HRST — SWTR —
Reset 1/0 0 1/0 0_0000
R/W Read/Write
Address MBAR + 0x000
Figure 6-3. Reset Status Register (RSR)