Datasheet

Chapter 6. SIM Overview 6-7
Programming Model
Figure 6-4. MCF5407 Embedded System Recovery from Unterminated Access
When the watchdog timer times out and SYPCR[SWRI] is programmed for a software
reset, an internal reset is asserted and RSR[SWTR] is set.
To prevent the watchdog timer from interrupting or resetting, the SWSR must be serviced
by performing the following sequence:
1. Write 0x55 to SWSR.
2. Write 0xAA to the SWSR.
Both writes must occur in order before the timeout, but any number of instructions or
SWSR accesses can be executed between the two writes. This order allows interrupts and
exceptions to occur, if necessary, between the two writes.
Caution should be exercised when changing SYPCR values after the software watchdog
timer has been enabled with the setting of SYPCR[SWE], because it is difficult to
determine the state of the watchdog timer while it is running. The countdown value is
constantly compared with the timeout period specified by SYPCR[SWP,SWT]. Therefore,
altering SWP and SWT improperly causes unpredictable processor behavior. The following
steps must be taken to change SWP or SWT:
Code enables software watchdog timer interrupt and
1. Watchdog timer times out due to unterminated bus
2. Watchdog timer interrupt cannot be serviced due to hung bus
cycle. Wait for another timeout before setting SYPCR[SWTA].
Timeout
Timeout
Software
SWTA functionality by writing SYPCR.
SYPCR[SWTAVAL]
1
Watchdog timer
3. TA held until another
bus cycle starts
Problem:
NOTE: The watchdog timer IRQ
should
be set to the highest level in the system.
1
SWTAVAL is set if watchdog timer TA is asserted.
Software
watchdog
timer IRQ
watchdog
timer TA
IACK cycle
Code in the watchdog timer interrupt
handler polls SYPCR[SWTAVAL] to
determine if SWT T
A was needed. If so,
execute code to identify bad address.