Datasheet

6-8 MCF5407 User’s Manual
Programming Model
1. Disable the software watchdog timer by clearing SYPCR[SWE].
2. Reset the counter by writing 0x55 and then 0xAA to SWSR.
3. Update SYPCR[SWT,SWP].
4. Reenable the watchdog timer by setting SYPCR[SWE]. This can be done in step 3.
6.2.5 System Protection Control Register (SYPCR)
The SYPCR, Figure 6-5, controls the software watchdog timer, timeout periods, and
software watchdog timer transfer acknowledge. The SYPCR can be read at any time, but
can be written only if a software watchdog timer IRQ
is not pending. At system reset, the
software watchdog timer is disabled.
Table 6-4 describes SYPCR fields.
76543210
Field SWE SWRI SWP SWT SWTA SWTAVAL —
Reset 0000_0000
R/W R/W
Address MBAR + 0x01
Figure 6-5. System Protection Control Register (SYPCR)
Table 6-4. SYPCR Field Descriptions
Bits Name Description
7 SWE Software watchdog timer enable
0 Software watchdog timer disabled
1 Software watchdog timer enabled
6 SWRI Software watchdog reset/interrupt select
0 If a timeout occurs, the watchdog timer generates an interrupt to the core processor at the
level programmed into ICR0[IL].
1 The software watchdog timer causes soft reset to be asserted for all modules of the part
except for the PLL (reset mode selects, such as PP_RESET_SEL or chip-select settings,
should not change).
5 SWP Software watchdog prescaler. This bit interacts with SYPCR[SWT].
0 Software watchdog timer clock not prescaled.
1 Software watchdog timer clock prescaled by 8192.
4–3 SWT Software watchdog timing delay. SWT and SWP select the timeout period for the watchdog
timer. At system reset, the software watchdog timer is set to the minimum timeout period.
SWP = 0
00 2
9
/system frequency
01 2
11
/system frequency
10 2
13
/system frequency
11 2
15
/system frequency
SWP = 1
00 2
22
/system frequency
01 2
24
/system frequency
10 2
26
/system frequency
11 2
28
/system frequency
Note that if SWP and SWT are modified to select a new software timeout, the software service
sequence must be performed (0x55 followed by 0xAA written to the SWSR) before the new
timeout period takes effect.