Datasheet

Chapter 6. SIM Overview 6-15
Programming Model
memories from responding to internal register transfers that go to the external bus.
The AS
signal and all chip-select-related strobe signals are not asserted.
Do not immediately follow a cycle in which SHOWDATA is set with a cycle using
fast termination.
• In multiple-master systems, disabling arbitration with EARBCTRL allows
performance improvement because internal register bus transfer cycles do not
interfere with the external bus.
Having internal transfers go external may affect performance in two ways:
— If the internal device does not control the bus immediately, the core stalls until it
wins arbitration of the external bus.
— If the core wins arbitration instantly, it may kick the external master off of the
external bus unnecessarily for a transfer that did not need the external bus. For
debug, where this performance penalty is not a concern, setting EARBCTRL and
SHOWDATA provides external visibility of the internal bus cycles.