Datasheet

7-2 MCF5407 User’s Manual
PLL Operation
Motorola recommends using CLKIN for the system clock. BCLKO is provided only for
compatibility with slower MCF5307 designs. Regardless of the CLKIN frequency driven
at power-up, CLKIN (and BCLKO) have the same ratio value to the PCLK. Although either
signal can be used as a clock reference, CLKIN leaves more room to meet the bus
specifications than BCLKO, which is generated as a phase-aligned signal to CLKIN.
7.1.1 PLL:PCLK Ratios
The PLL for the MCF5407 is enhanced to support faster processor clock (PCLK)
frequencies. While the MCF5307 supports various PCLK frequencies listed in the electrical
specifications with a clock input (CLKIN) of 1/2 PCLK, the MCF5407 offers a wider range
of clock input ratios and a higher performance processor clock.
Like the MCF5307, the MCF5407 samples clock ratio encodings on the lower data bus bits
at reset to determine the CLKIN-to-PCLK ratio. These bits are DIVIDE[1:0] on the
MCF5307 and are multiplexed with data bits D[1:0]. Because the MCF5407 offers more
divide ratio than the MCF5307, three bits, D[2:0]/DIVIDE[2:0], are provided to offer more
programming options at reset. Also, note that only specific CLKIN ranges are allowed for
each divide ratio on the MCF5407. Table 7-1 shows MCF5407 divide ratio encodings.
7.2 PLL Operation
The following sections provide detailed information about the three PLL modes.
7.2.1 Reset/Initialization
The PLL receives RSTI as an input directly from the pin. Additionally, signals are
multiplexed with D[2:0]/DIVIDE[2:0] while RSTI
is asserted. These signals are sampled
during reset and registered by the PLL on the negation of RSTI
to provide initialization
information. DIVIDE[2:0] are used by the PLL to set the CLKIN/PCLK ratio.
7.2.2 Normal Mode
CLKIN should be used as the system bus clock in 5407 systems. The CLKIN frequency is
Table 7-1. Divide Ratio Encodings
D[2:0]/DIVIDE[2:0] Multiplier
00x–010 Reserved
011 3
100 4
101 5
110 6
111 Reserved