Datasheet

Chapter 8. I
2
C Module 8-3
I
2
C System Configuration
These registers are described in Section 8.5, “Programming Model.”
8.3 I
2
C System Configuration
The I
2
C module uses a serial data line (SDA) and a serial clock line (SCL) for data transfer.
For I
2
C compliance, all devices connected to these two signals must have open drain or
open collector outputs. (There is no such requirement for inputs.) The logic AND function
is exercised on both lines with external pull-up resistors.
Out of reset, the I
2
C default is as slave receiver. Thus, when not programmed to be a master
or responding to a slave transmit address, the I
2
C module should return to the default slave
receiver state. See Section 8.6.1, “Initialization Sequence,” for exceptions.
NOTE:
The I
2
C module is designed to be compatible with the Philips
I
2
C bus protocol. For information on system configuration,
protocol, and restrictions, see The I
2
C Bus Specification,
Version 2.1.
8.4 I
2
C Protocol
Normally, a standard communication is composed of the following parts:
1. START signal—When no other device is bus master (both SCL and SDA lines are
at logic high), a device can initiate communication by sending a START signal (see
A in Figure 8-2). A START signal is defined as a high-to-low transition of SDA
while SCL is high. This signal denotes the beginning of a data transfer (each data
transfer can be several bytes long) and awakens all slaves.
Figure 8-2. I
2
C Standard Communication Protocol
2. Slave address transmission—The master sends the slave address in the first byte
after the START signal (B). After the seven-bit calling address, it sends the R/W bit
(C), which tells the slave data transfer direction.
12345678 123456789 9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0
Calling Address
R/W
ACK
Bit
Data Byte
No
ACK
Bit
STOP
Signal
lsbmsblsbmsb
SDA
SCL
START
Signal
A
B
DC
E
F