Datasheet

Chapter 9. Interrupt Controller 9-7
Interrupt Controller Registers
Table 9-7 describes IPR and IMR fields.
9.2.4 Interrupt Port Assignment Register (IRQPAR)
The interrupt port assignment register (IRQPAR), shown in Figure 9-5, provides the level
assignment of the primary external interrupt pins—IRQ5, IRQ3, and IRQ1. The setting of
IRQPAR2–IRQPAR0 determines the interrupt level of these external interrupt pins.
Table 9-8 describes IRQPAR fields.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field — DMA3 DMA2
Reset —
1
1
R/W Read-only (IPR); R/W (IMR)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field DMA1 DMA0 UART1 UART0 I2C TIMER2 TIMER1 SWT EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 —
Reset 1111 1111 1111 1 1 1 —
R/W Read-only (IPR); R/W (IMR)
Addr MBAR + 0x040 (IPR); + 0x044 (IMR)
Figure 9-4. Interrupt Pending Register (IPR) and Interrupt Mask Register (IMR)
Table 9-7. IPR and IMR Field Descriptions
Bits Name Description
31–18 — Reserved, should be cleared.
17–1 See
Figure
9-4
Interrupt pending/mask. Each bit corresponds to an interrupt source defined by the ICR. The
corresponding IMR bit determines whether an interrupt condition can generate an interrupt. At
every clock, the IPR samples the signal generated by the interrupting source. The corresponding
IPR bit reflects the state of the interrupt signal even if the corresponding IMR bit is set.
0 The corresponding interrupt source is not masked (IMR) and has no interrupt pending (IPR).
1 The corresponding interrupt source is masked (IMR) and has an interrupt pending (IPR)
76543210
Field IRQPAR2 IRQPAR1 IRQPAR0 — ENBDACK1 ENBDACK0
Reset 0000_0000
R/W R/W
Address MBAR + 0x06
Figure 9-5. Interrupt Port Assignment Register (IRQPAR)