Datasheet

9-8 MCF5407 User’s Manual

Interrupt Controller Registers

Table 9-8. IRQPAR Field Descriptions

Bits Name Description

7–5 IRQPARn Conﬁgures the IRQ pin assignments and priorities

IRQPARn External Pin IRQPARn = 0 IRQPARn = 1

IRQPAR2 IRQ5 Level 5 Level 4

IRQPAR1 IRQ3 Level 3 Level 6

IRQPAR0 IRQ1 Level 1 Level 2

4–2 — Reserved, should be cleared.

1–0 ENBDACKn Enable D

ACK1 and DACK0. Determines the functionality of the respective TMn/DACKn pins.

0 TM1 and TM0 are driven instead of D

ACK1 and DACK0.

1 If the PAR register is programmed to enable TMn, the D

ACKn signal for DMA channel n is

driven in place of TMn for DMA transfers.