Datasheet

Chapter 10. Chip-Select Module 10-5
Chip-Select Registers
Provided the required address range is in the chip-select address register (CSAR0), CS0 can
be programmed to continue decoding for a range of addresses after the CSMR0[V] is set,
after which the global chip-select can be restored only by a system reset.
10.4 Chip-Select Registers
Table 10-7 is the chip-select register memory map. Reading reserved locations returns
zeros.
Table 10-5. D[6:5]/PS[1:0], Port Size of Boot CS0
D[6:5]/PS[1:0] Boot CS0 Port Size at Reset
00 32-bit port
01 8-bit port
1x 16-bit port
Table 10-6. D3/BE_CONFIG0, BE[3:0] Boot Configuration
D3/BE_CONFIG0 Configuration of Byte Enables for Boot CS0
0BE[3:0] is enabled as byte write enables only.
1BE
[3:0] is enabled as byte enables for reads and writes.
Table 10-7. Chip-Select Registers
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x080 Chip-select address register—bank 0 (CSAR0) [p. 10-6] Reserved
1
0x084 Chip-select mask register—bank 0 (CSMR0) [p. 10-7]
0x088 Reserved
1
Chip-select control register—bank 0
(CSCR0) [p. 10-8]
0x08C Chip-select address register—bank 1 (CSAR1) [p. 10-6] Reserved
1
0x090 Chip-select mask register—bank 1 (CSMR1) [p. 10-7]
0x094 Reserved
1
Chip-select control register—bank 1
(CSCR1) [p. 10-8]
0x098 Chip-select address register—bank 2 (CSAR2) [p. 10-6] Reserved
1
0x09C Chip-select mask register—bank 2 (CSMR2) [p. 10-7]
0x0A0 Reserved
1
Chip-select control register—bank 2
(CSCR2) [p. 10-8]
0x0A4 Chip-select address register—bank 3 (CSAR3) [p. 10-6] Reserved
1
0x0A8 Chip-select mask register—bank 3 (CSMR3) [p. 10-7]
0x0AC Reserved
1
Chip-select control register—bank 3
(CSCR3) [p. 10-8]
0x0B0 Chip-select address register—bank 4 (CSAR4) [p. 10-6] Reserved
1
0x0B4 Chip-select mask register—bank 4 (CSMR4) [p. 10-7]