Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-5
Asynchronous Operation
Table 11-3 describes DCR fields.
11.3.2.2 DRAM Address and Control Registers (DACR0/DACR1)
DACR0 and DACR1, Figure 11-3, contain the base address compare value and the control
bits for memory blocks 0 and 1. Address and timing are also controlled by these registers.
Memory areas defined for each block should not overlap; operation is undefined for
accesses in overlapping regions.
15 14 13 12 11 10 9 8 0
Field SO — NAM RRA RRP RC
Reset 0 Uninitialized
R/W R/W
Address MBAR + 0x100
Figure 11-2. DRAM Control Register (DCR) (Asynchronous Mode)
Table 11-3. DCR Field Descriptions (Asynchronous Mode)
Bits Name Description
15 SO Synchronous operation. Selects synchronous or asynchronous mode. A DRAM controller in
synchronous mode can be switched to ADRAM mode only by resetting the MCF5407.
0 Asynchronous DRAMs. Default at reset.
1 Synchronous DRAMs
14 — Reserved, should be cleared.
13 NAM No address multiplexing. Some implementations require external multiplexing. For example, when
linear addressing is required, the DRAM should not multiplex addresses on DRAM accesses.
0 The DRAM controller multiplexes the external address bus to provide column addresses.
1 The DRAM controller does not multiplex the external address bus to provide column addresses.
12–11 RRA Refresh RAS
asserted. Determines how long RAS is asserted during a refresh operation.
00 2 clocks
01 3 clocks
10 4 clocks
11 5 clocks
10–9 RRP Refresh RAS
precharge. Controls how many clocks RAS is precharged after a refresh operation
before accesses are allowed to DRAM.
00 1 clock
01 2 clocks
10 3 clocks
11 4 clocks
8–0 RC Refresh count. Controls refresh frequency. The number of bus clocks between refresh cycles is
(RC + 1) * 16. Refresh can range from 16–8192 bus clocks to accommodate both standard and
low-power DRAMs with bus clock operation from less than 2 MHz to greater than 50 MHz.
The following example calculates RC for an auto-refresh period for 4096 rows to receive 64 mS of
refresh every 15.625 µs for each row (625 bus clocks at 40 MHz).
# of bus clocks = 625 = (RC field + 1) * 16
RC = (625 bus clocks/16) -1 = 38.06, which rounds to 38; therefore, RC = 0x26.