Datasheet

11-6 MCF5407 User’s Manual
Asynchronous Operation
Table 11-4 describes DACRn fields.
31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field BA — RE — CAS RP RNCN RCD — EDO PS PM —
Reset Unitialized 0 Unitialized
R/W R/W
Addr MBAR + 0x10C (DACR0); 0x110 (DACR1)
Figure 11-3. DRAM Address and Control Registers (DACR0/DACR1)
Table 11-4. DACR0/DACR1 Field Description
Bits Name Description
31–18 BA Base address. Used with DMR[BAM] to determine the address range in which the associated
DRAM block is located. Each BA bit is compared with the corresponding address of the bus cycle in
progress. If each bit matches, or if bits that do not match are masked in the BAM, the address
selects the associated DRAM block.
17–16 — Reserved, should be cleared.
15 RE Refresh enable. Determines whether the DRAM controller generates a refresh to the associated
DRAM block. DRAM contents are not preserved during hard reset or software watchdog reset.
0 Do not refresh associated DRAM block. (Default at reset)
1 Refresh associated DRAM block.
14 — Reserved, should be cleared.
13–12 CAS CAS
timing. Determines how long CAS is asserted during a DRAM access.
00 1 clock cycle
01 2 clock cycles
10 3 clock cycles
11 4 clock cycles
11–10 RP RAS
precharge timing. Determines how long RAS is precharged between accesses. Note that RP
is different from DCR[RRP].
00 1 clock cycle
01 2 clock cycles
10 3 clock cycles
11 4 clock cycles
9 RNCN RAS
-negate-to-CAS-negate. Controls whether RAS and CAS negate concurrently or one clock
apart. RNCN is ignored if CAS
is asserted for only one clock and both RAS and CAS are negated.
RNCN is used only for non-page-mode accesses and single accesses in page mode.
0 RAS
negates concurrently with CAS.
1 RAS
negates one clock before CAS.
8 RCD RAS
-to-CAS delay. Determines the number of system clocks between assertions of RAS and CAS.
0 1 clock cycle
1 2 clock cycles
7 — Reserved, should be cleared.
6 EDO Extended data out. Determines whether the DRAM block operates in a mode to take advantage of
industry-standard EDO DRAMs. Do not use EDO mode with non-EDO DRAM.
0 EDO operation disabled.
1 EDO operation enabled.