Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-7
Asynchronous Operation
11.3.2.3 DRAM Controller Mask Registers (DMR0/DMR1)
The DRAM controller mask registers (DMR0 and DMR1), shown in Figure 11-4, include
mask bits for the base address and for address attributes.
Table 11-5 describes DMRn fields.
5–4 PS Port size. Determines the port size of the associated DRAM block. For example, if two 16-bit wide
DRAM components form one DRAM block, the port size is 32 bits. Programming PS allows the
DRAM controller to execute dynamic bus sizing for associated accesses.
00 32-bit port
01 8-bit port
1x 16-bit port
3–2 PM Page mode. Configures page-mode operation for the memory block.
00 No page mode
01 Burst page mode (page mode for bursts only)
10 Reserved
11 Continuous page mode
1–0 — Reserved, should be cleared.
31 1817 9876543210
Field BAM — WP — C/I AM SC SD UC UD V
Reset Uninitialized 0
R/W R/W
Addr MBAR + 0x10C (DMR0), 0x114 (DMR1)
Figure 11-4. DRAM Controller Mask Registers (DMR0 and DMR1)
Table 11-5. DMR0/DMR1 Field Descriptions
Bits Name Description
31–18 BAM Base address mask. Masks the associated DACRn[BA]. Lets the DRAM controller connect to various
DRAM sizes. Mask bits need not be contiguous (see Section 11.5, “SDRAM Example.”)
0 The associated address bit is used in decoding the DRAM hit to a memory block.
1 The associated address bit is not used in the DRAM hit decode.
17–9 — Reserved, should be cleared.
8 WP Write protect. Determines whether the associated block of DRAM is write protected.
0 Allow write accesses
1 Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an
address exception occurs. Write accesses to a write-protected DRAM region are compared in the
chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus
cycle is not acknowledged, an access exception occurs.
7 — Reserved, should be cleared.
Table 11-4. DACR0/DACR1 Field Description (Continued)
Bits Name Description