Datasheet

11-12 MCF5407 User’s Manual
Asynchronous Operation
Figure 11-6 shows a variation of the basic cycle. In this case, RCD is 1, so there are two
clocks between RAS
and CAS. Note that the address is multiplexed on the rising clock
immediately before CAS
is asserted. Because RNCN = 0, RAS and CAS are negated
together. The next bus cycle is initiated, but because DACRn[RP] requires RAS
to be
precharged for two clocks, RAS
is delayed for a clock in the bus cycle. Note that this does
not delay the address signals, only RAS
.
Figure 11-6. Basic Non-Page-Mode Operation RCD = 1, RNCN = 0 (5-5-5-5)
11.3.3.2 Burst Page-Mode Operation
Burst page-mode operation (DACRn[PM] = 01) optimizes memory accesses in page mode
by allowing a row address to remain registered in the DRAM while accessing data in
different columns. This eliminates the setup and hold times associated with the need to
precharge and assert RAS. Therefore, only the first bus cycle in the page takes the full
access time; subsequent accesses are streamlined. Single accesses look the same as
non-page-mode accesses.
Burst page-mode accesses of any size—byte, word, longword, or line—are assumed to
reside in the same page. In this mode, the DRAM controller generates a burst transfer only
when the operand is larger than the DRAM block port size (such as, a line transfer to a
32-bit port or a longword transfer to an 8-bit port). The primary cycle asserts RAS
and
CAS
; subsequent cycles assert only CAS. At the end of the access, RAS is precharged. The
DRAM controller increments addresses between cycles.
Figure 11-7 shows a read access in burst page mode. Four accesses take place, which could
be a 32-bit access to an 8-bit port or a line access to a 32-bit port. Other burst page-mode
operations may be from 2 to 16 accesses long, depending on the access and port sizes. In
those cases, timing is similar with more or fewer accesses.
A[31:0]
RAS[1] or [0]
CAS[3:0]
DRAMW
D[31:0]
RCD = 1 RNCN = 0
CAS = 01
RP = 01
Row Column
CLKIN