Datasheet

11-16 MCF5407 User’s Manual
Synchronous Operation
11.3.3.5 Refresh Operation
The DRAM controller supports CAS-before-RAS refresh operations that are not
synchronized to bus activity. A special DRAMW
pin is provided so refresh can occur
regardless of the state of the processor bus.
When the refresh counter rolls over, it sets an internal flag to indicate that a refresh is
pending. If that happens during a continuous page-mode access, the page is closed (RAS
precharged) when the data transfer completes to allow the refresh to occur. The flag is
cleared when the refresh cycle is run. Both memory blocks are simultaneously refreshed as
determined by the DCR. DRAM accesses are delayed during refresh. Only an active bus
access to a DRAM block can delay refresh.
Figure 11-12 shows a bus cycle delayed by a refresh operation. Notice that DRAMW
is
forced high during refresh. The row address is held until the pending DRAM access.
Figure 11-12. DRAM Access Delayed by Refresh
11.4 Synchronous Operation
By running synchronously with the system clock instead of responding to asynchronous
control signals, SDRAM can (after an initial latency period) be accessed on every clock;
5-1-1-1 is a typical MCF5407 burst rate to SDRAM.
Note that because the MCF5407 cannot have more than one page open at a time, it does not
support interleaving.
SDRAM controllers are more sophisticated than asynchronous DRAM controllers. Not
only must they manage addresses and data, but they must send special commands for such
functions as precharge, read, write, burst, auto-refresh, and various combinations of these
functions. Table 11-10 lists common SDRAM commands.
A[31:0]
RAS
[1] or [0]
CAS
[3:0]
DRAMW
RRA = 01
RRP = 01
CLKIN
Refresh Access