Datasheet

11-28 MCF5407 User’s Manual
Synchronous Operation
latency (SCAS assertion to data out), this value is also 2 CLKIN cycles. Notice that NOPs
are executed until the last data is read. A
PALL command is executed one cycle after the last
data transfer.
Figure 11-18. Burst Read SDRAM Access
Figure 11-19 shows the burst write operation. In this example, DACR[CASL] = 01, which
creates an SRAS
-to-SCAS delay (t
RCD
) of 2 CLKIN cycles. Note that data is available
upon SCAS
assertion and a burst write cycle completes two cycles sooner than a burst read
cycle with the same t
RCD.
The next bus cycle is initiated sooner, but cannot begin an
SDRAM cycle until the precharge-to-
ACTV delay completes.
A[31:0]
SRAS
SCAS
DRAMW
D[31:0]
t
CASL
= 2
ACTV READ NOPNOP
RAS[0] or [1]
CAS
[3:0]
NOP PALL
Row Column Column Column Column
t
RCD
= 2
t
EP
CLKIN