Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-29
Synchronous Operation
Figure 11-19. Burst Write SDRAM Access
Accesses in synchronous burst page mode always cause the following sequence:
1.
ACTV command
2.
NOP commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no
NOP commands).
3. Required number of
READ or WRITE commands to service the transfer size with the
given port size.
4. Some transfers need more
NOP commands to assure the ACTV-to-precharge delay.
5.
PALL command
6. Required number of idle clocks inserted to assure precharge-to-
ACTV delay.
11.4.4.4 Continuous Page Mode
Continuous page mode is identical to burst page mode, except that it allows the processor
core to handle successive bus cycles that hit the same page without having to close the page.
When the current bus cycle finishes, the MCF5407 core internal pipelined bus can predict
whether the upcoming cycle will hit in the same page.
• If the next bus cycle is not pending or misses in the page, the
PALL command is
generated to the SDRAM.
A[31:0]
S
RAS
SCAS
DRAMW
D[31:0]
ACTV WRITE PALLNOP
RAS[0] or [1]
CAS[3:0]
t
CASL
= 2
Row Column Column Column Column
t
RP
t
RWL
CLKIN
NOP