Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-31
Synchronous Operation
Figure 11-21. Synchronous, Continuous Page-Mode Access—Read after Write
11.4.4.5 Auto-Refresh Operation
The DRAM controller is equipped with a refresh counter and control. This logic is
responsible for providing timing and control to refresh the SDRAM. Once the refresh
counter is set, and refresh is enabled, the counter counts to zero. At this time, an internal
refresh request flag is set and the counter begins counting down again. The DRAM
controller completes any active burst operation and then performs a
PALL operation. The
DRAM controller then initiates a refresh cycle and clears the refresh request flag. This
refresh cycle includes a delay from any precharge to the auto-refresh command, the
auto-refresh command, and then a delay until any
ACTV command is allowed. Any SDRAM
access initiated during the auto-refresh cycle is delayed until the cycle is completed.
Figure 11-22 shows the auto-refresh timing. In this case, there is an SDRAM access when
the refresh request becomes active. The request is delayed by the precharge to
ACTV delay
programmed into the active SDRAM bank by the CAS bits. The
REF command is then
generated and the delay required by DCR[RTIM] is inserted before the next
ACTV
command is generated. In this example, the next bus cycle is initiated, but does not generate
an SDRAM access until T
RC
is finished. Because both chip selects are active during the REF
command, it is passed to both blocks of external SDRAM.
A[31:0]
SRAS
SCAS
DRAMW
D[31:0]
ACTV NOP READNOP
RAS[0] or [1]
CAS[3:0]
WRITE NOP
NOP
NOP PALL
Row Column
Column
t
CASL
= 3
t
RCD
= 3
t
EP
CLKIN