Datasheet

11-34 MCF5407 User’s Manual
SDRAM Example
access can be a read or write. The important thing is that the address output of that access
needs the correct mode programming information on the correct address bits.
Figure 11-24 shows the
MRS command, which occurs in the first clock of the bus cycle.
Figure 11-24. Mode Register Set (MRS) Command
11.5 SDRAM Example
This example interfaces a 2M x 32-bit x 4 bank SDRAM component to a MCF5407
operating at 40 MHz. Table 11-32 lists design specifications for this example.
11.5.1 SDRAM Interface Confi guration
To interface this component to the MCF5407 DRAM controller, use the connection table
that corresponds to a 32-bit port size with 8 columns (Table 11-26). Two pins select one of
four banks when the part is functional. Table 11-33 shows the proper hardware hook-up.
Table 11-32. SDRAM Example Specifications
Parameter Specification
Speed grade (-8E) 40 MHz (25-nS period)
10 rows, 8 columns
Two bank-select lines to access four internal banks
ACTV-to-read/write delay (t
RCD
) 20 nS (min.)
Period between auto refresh and
ACTV command (t
RC
) 70 nS
ACTV command to precharge command (t
RAS
) 48 nS (min.)
Precharge command to
ACTV command (t
RP
) 20 nS (min.)
Last data input to
PALL command (t
RWL
) 1 bus clock (25 nS)
Auto refresh period for 4096 rows (t
REF
) 64 mS
A[31:0]
SRAS
, SCAS
DRAMW
D[31:0]
MRS
RAS[1] or [0]
CLKIN