Datasheet

12-2 MCF5407 User’s Manual
DMA Signal Description
12.1.1 DMA Module Features
The DMA controller module features are as follows:
• Four fully independent, programmable DMA controller channels/bus modules
• Auto-alignment feature for source or destination accesses
• Dual- and single-address transfers
• Two external request pins (DREQ
[1:0]) provided for channels 1 and 0
• Two external acknowledge pins (DACK[1:0]) provided for channels 1 and 0
• Channels 2 and 3 have request signals connected to the interrupt lines of UART0 and
UART1, programmable through the channel select field MODCTL[DSL]. See
Section 14.3.4, “Modem Control Register (MODCTL).”
• Channel arbitration on transfer boundaries
• Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
• Continuous-mode and cycle-steal transfers
• Independent transfer widths for source and destination
• Independent source and destination address registers
• Data transfer can occur in as few as two clocks
12.2 DMA Signal Description
Table 12-1 briefly describes the DMA module signals that provide handshake control for
either a source or destination external device.
Table 12-1. DMA Signals
Signal I/O Description
DREQ
[1:0]/
PP[6:5]
I External DMA request. DREQ[1:0] can serve as the DMA request inputs or as two parallel port
bits. They are programmable individually through the PAR. A peripheral device asserts these
inputs to request an operand transfer between it and memory.
DREQ
signals are asserted to initiate DMA accesses in the respective channels. The system
should drive unused DREQ
signals to logic high. Although each channel has an individual
DREQ
signal, in the MCF5407 only channels 0 and 1 connect to external DREQ pins. DREQ2
and DREQ3
are programmable for use with UART0 and UART1 through MODCTL[DSL]. See
Section 14.3.4, “Modem Control Register (MODCTL).”
TT[1:0]/
PP[1:0]
O Transfer type. A DMA access is indicated by the transfer type pins, TT[1:0] = 01. The transfer
modifier, TM[2:0], and DMA acknowledgement, DACK[1:0], configurations shown below are
meaningful only if TT[1:0] = 01, indicating an external master or DMA access.