Datasheet

Chapter 12. DMA Controller Module 12-3
DMA Signal Description
Table 12-2 shows MCF5407 pin configurations based on PAR and IRQPAR configurations.
Designers who used MCF5307 DMA channels should also note that the DMA byte count
registers (BCR) for channels 0–3 exclusively support a 24-bit byte count. A 16-bit byte
count register and MPARK[BCR24BIT] are no longer supported.
As shown in Figure 12-2, when properly connected, TM[2:0] can be used in MCF5407
designs in the same manner as they were on MCF5307 designs or DACK[1:0] can be used
for DMA transfers.
TM[2:0]/
DACK[1:0]
O Transfer modifier/DMA acknowledge. The MCF5407 TM[2:0] encodings are like the MCF5307,
with functions shifted slightly, as Figure 12-2 shows. Dedicated DMA acknowledgement pins,
DACK[1:0], are added and multiplexed as follows—TM[1:0]/DACK[1:0]/PP[3:2]. TM2 is still
multiplexed only with PP4. Chapter 17, “Signal Descriptions,” describes multiplexing.
Although on the MCF5407, TM[2:0] can be programmed to be DMA acknowledge signals, bit
positions of these encodings differ from the MCF5307. Single-address access indication is now
encoded on TM2 when the PAR is set to enable the transfer modifier signal and an external or
DMA transfer is occurring. This encoding is driven by TM0 on the MCF5307. In addition, DMA
acknowledge signals are multiplexed with TM[1:0] on the MCF5407, as opposed to TM[2:1]
providing DMA transfer information on the MCF5307. The MCF5407 encoding for TM[2:0],
shown below describes when PAR is set to enable these signals and the IRQPAR is
programmed to disable DACK[1:0]. Note that when DACK[1:0] are driven, TM2 is still driven if it
is enabled through the PAR.
To enable DACK[1:0], first enable TM[1:0] and then program the interrupt assignment register
(IRQPAR) to enable bits 0–1. When IRQPAR[ENBDACK1] = 1 and TM1 is enabled, DACK1 for
DMA channel 1 is driven in place of TM1 for DMA transfers. Clearing ENBDACK1 disables this
function and only the TM1 encoding is driven. Likewise, setting ENBDACK0 enables DACK0 to
be driven; clearing ENBDACK0 disables this function and drives the TM0 encoding.
TM2 Encoding
0 Single-address access negated
1 Single-address access
TM[1:0] Encoding
00 DMA acknowledge information not provided
01 DMA transfer, channel 0
10 DMA transfer, channel 1
11 Reserved
The DMA transfer information on TM[1:0] can be provided on every DMA transfer or only on the
last transfer by programming DCR[AT].
DACK[1:0] I/O DMA acknowledge. These signals provide an acknowledge of a DMA transfer. They can be
programmed using DCR[AT] to assert on every transfer or only on the final transfer.
Table 12-2. MCF5407 Signal Configurations for PP[4:2]/TM[2:0]/DACK[1:0]
PAR
Configuration
1
1
Note that to enable DACK[1:0], PAR must first be programmed to enable TM[1:0].
IRQPAR Configuration PP[4:2] TM[2:0] DACK[1:0]
TM[2:0] disabled,
PP[4:2] enabled
ENBDACK[1–0] = 0 or 1 Driven Not driven Not driven
TM[2:0] enabled ENBDACK[1–0] = 0 Not driven TM[2:0] driven Not driven
TM[2:0] enabled ENBDACK[1–0] = 1 Not driven TM2 driven only Driven
Table 12-1. DMA Signals (Continued)
Signal I/O Description