Datasheet

12-4 MCF5407 User’s Manual
DMA Transfer Overview
Figure 12-2. MCF5307/MCF5407 TM[2:0] Pin Remapping
12.3 DMA Transfer Overview
The DMA module usually transfers data faster than the ColdFire core can under software
control. The term ‘direct memory access’ refers to peripheral device’s ability to access
system memory directly, greatly improving overall system performance. The DMA module
consists of four independent, functionally equivalent channels, so references to DMA in
this chapter apply to any of the channels. It is not possible to implicitly address all four
channels at once. The MCF5407 on-chip peripherals do not support single-address
transfers.
The processor generates DMA requests internally by setting DCR[START]; a device can
generate a DMA request externally by using DREQ
pins. The processor can program bus
bandwidth for each channel. The channels support cycle-steal and continuous transfer
modes; see Section 12.5.1, “Transfer Requests (Cycle-Steal and Continuous Modes).”
The DMA controller supports dual- and single-address transfers as follows. In both, the
DMA channel supports 32 address bits and 32 data bits.
• Dual-address transfers—A dual-address transfer consists of a read followed by a
write and is initiated by an internal request using the START bit or by an external
device using DREQ
. Two types of transfer can occur, a read from a source device or
a write to a destination device; see Figure 12-3.
Figure 12-3. Dual-Address Transfer
MCF5307 Function Pin Pin MCF5407 Function
Single/dual cycle access TM0 TM0 DMA 0 acknowledge
DMA 0 acknowledge configuration TM1 TM1 DMA 1 acknowledge
DMA 1 acknowledge configuration TM2 TM2 Single/dual cycle access
DMADMA
Memory/
Peripheral
Memory/
Peripheral
Control and Data
Control and Data