Datasheet

Chapter 12. DMA Controller Module 12-5
DMA Controller Module Programming Model
• Single-address transfers—An external device can initiate a single-address transfer
by asserting DREQ
. The MCF5407 provides address and control signals for
single-address transfers. The external device reads to or writes from the specified
address, as Figure 12-4 shows. External logic is required.
Figure 12-4. Single-Address Transfers
Any operation involving the DMA module follows the same three steps:
1. Channel initialization—Channel registers are loaded with control information,
address pointers, and a byte-transfer count.
2. Data transfer—The DMA accepts requests for operand transfers and provides
addressing and bus control for the transfers.
3. Channel termination—Occurs after the operation is finished, either successfully or
due to an error. The channel indicates the operation status in the channel’s DSR,
described in Section 12.4.5, “DMA Status Registers (DSR0–DSR3).”
12.4 DMA Controller Module Programming Model
This section describes each internal register and its bit assignment. Note that there is no way
to prevent a write to a control register during a DMA transfer. Table 12-3 shows the
mapping of DMA controller registers.
DMA
Memory
DMA
Peripheral
Control Signals Control Signals
Control Signals Control Signals
Data
Memory Peripheral
Data
Write:
Read: