Datasheet

12-6 MCF5407 User’s Manual
DMA Controller Module Programming Model
NOTE:
External masters cannot access MCF5407 on-chip memories or
MBAR, but they can access DMA module registers.
Table 12-3. Memory Map for DMA Controller Module Registers
DMA
Channel
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0 0x300 Source address register 0 (SAR0) [p. 12-7]
0x304 Destination address register 0 (DAR0) [p. 12-7]
0x308 DMA control register 0 (DCR0) [p. 12-8]
0x30C Reserved Byte count register 0 (BCR0) [p. 12-7]
0x310 DMA status register 0
(DSR0) [p. 12-10]
Reserved
0x314 DMA interrupt vector
register 0 (DIVR0)
[p. 12-11]
Reserved
1 0x340 Source address register 1 (SAR1) [p. 12-7]
0x344 Destination address register 1 (DAR1) [p. 12-7]
0x348 DMA control register 1 (DCR1) [p. 12-8]
0x34C Reserved Byte count register 1
(BCR1) [p. 12-7]
0x350 DMA status register 1
(DSR1) [p. 12-10]
Reserved
0x354 DMA interrupt vector
register 1 (DIVR1)
[p. 12-11]
Reserved
2 0x380 Source address register 2 (SAR2) [p. 12-7]
0x384 Destination address register 2 (DAR2) [p. 12-7]
0x388 DMA control register 2 (DCR2) [p. 12-8]
0x38C Reserved Byte count register 2 (BCR2) [p. 12-7]
0x390 DMA status register 2
(DSR2) [p. 12-10]
Reserved
0x394 DMA interrupt vector
register 2 (DIVR2)
[p. 12-11]
Reserved
3 0x3C0 Source address register 3 (SAR3) [p. 12-7]
0x3C4 Destination address register 3 (DAR3) [p. 12-7]
0x3C8 DMA control register 3 (DCR3) [p. 12-8]
0x3CC Reserved Byte count register 3 (BCR3) [p. 12-7]
0x3D0 DMA status register 3
(DSR3) [p. 12-10]
Reserved
0x3D4 DMA interrupt vector
register 3 (DIVR3)
[p. 12-11]
Reserved