Datasheet

12-12 MCF5407 User’s Manual
DMA Controller Module Functional Description
12.5.1 Transfer Requests (Cycle-Steal and Continuous
Modes)
The DMA channel supports internal and external requests. A request is issued by setting
DCR[START] or by asserting DREQ
. Setting DCR[EEXT] enables recognition of external
interrupts. Internal interrupts are always recognized. Bus usage is minimized for either
internal or external requests by selecting between cycle-steal and continuous modes.
• Cycle-steal mode (DCR[CS] = 1)—Only one complete transfer from source to
destination occurs for each request. If DCR[EEXT] is set, a request can be either
internal or external. Internal request is selected by setting DCR[START]. An
external request is initiated by asserting DREQ
while EEXT is set.
• Continuous mode (DCR[CS] = 0)—After an internal or external request, the DMA
continuously transfers data until BCR reaches zero or a multiple of DCR[BWC] or
DSR[DONE] is set. If BCR is a multiple of BWC, the DMA request signal is
negated until the bus cycle terminates to allow the internal arbiter to switch masters.
DCR[BWC] = 000 specifies the maximum transfer rate; other values specify a
transfer rate limit.
The DMA performs the specified number of transfers, then relinquishes bus control.
The DMA negates its internal bus request on the last transfer before the BCR reaches
a multiple of the boundary specified in BWC. On completion, the DMA reasserts its
bus request to regain mastership at the earliest opportunity. The minimum time that
the DMA loses bus control is one bus cycle.
12.5.2 Data Transfer Modes
Each channel supports dual- and single-address transfers, described in the next sections.
12.5.2.1 Dual-Address Transfers
Dual-address transfers consist of a source operand read and a destination operand write.
The DMA controller module begins a dual-address transfer sequence when DCR[SAA] is
cleared during a DMA request. If no error condition exists, DSR[REQ] is set.
• Dual-address read—The DMA controller drives the SAR value onto the internal
address bus. If DCR[SINC] is set, the SAR increments by the appropriate number
of bytes upon a successful read cycle. When the appropriate number of read cycles
complete (multiple reads if the destination size is wider than the source), the DMA
initiates the write portion of the transfer.
If a termination error occurs, DSR[BES,DONE] are set and DMA transactions stop.
• Dual-address write—The DMA controller drives the DAR value onto the address
bus. If DCR[DINC] is set, DAR increments by the appropriate number of bytes at
the completion of a successful write cycle. The BCR decrements by the appropriate
number of bytes. DSR[DONE] is set when BCR reaches zero. If the BCR is greater